As field effect transistors have been scaled down to submicron levels, short-channel effects have become a major concern. Punchthrough, which is defined as current leakage through the channel of a field-effect transistor when the gate voltage is coupled to the source, is one such short-channel effect. In order to mitigate the punchthrough phenomenon, the transistor channel is implanted with an impurity that is of the opposite conduction type as that implanted in the source and drain regions. For example, boron or boron compounds are typically implanted into the channels of N-channel devices, while phosphorus is typically implanted into the channels of P-channel devices.
A simple method for dealing with the punchthrough problem calls for the implanting of boron, at an energy of about 50 kev and a dosage of about 4E12, into active areas following wordline patterning. The boron implant is thus aligned to the edges of the transistor gates. Following the deposition of a thin offsetting dielectric layer, a low-dosage N-type implant is performed. Phosphorus is typically used for such implants. Thermal steps during the remainder of the fabrication process drive the boron atoms and phosphorus atoms into the substrate at similar rates. The desired final location of the diffusion front for the low-dosage N-type implant slightly underlaps the gate edges. The boron implant, therefore, underlaps the gate edges to a greater degree. This simple approach has several drawbacks. One drawback is that boron is implanted into both source/drain regions of the transistor. Since one of the boron-implanted source/drain regions must function as the storage node of the DRAM cell, there is a significant degradation of static refresh parameters due to the leakage of stored charge across the diode junction into the substrate. This problem is compounded by the overlap of the boron field implant and the storage node boron implant, and is particularly acute where the field edge meets the transistor gate edge.
The solutions to the above-described problem have hitherto included masking the storage node region during the boron implant or performing no boron anti-punchthrough implant at all. The problem with the first solution is that fabrication costs are increased due to the use of an additional masking step. The problem with the second solution is that capacitor leakage through the storage-node diode into the substrate is traded for capacitor leakage through the access transistor to the digit line. In addition, the absence of the boron punchthrough implant also tends to promote gate-induced diode leakage, a phenomenon that is generally not characterized as a short-channel effect.
What is needed is a new process that will eliminate the boron from the storage node junction without the use of an additional mask, which will prevent the encroachment of the field implant into the storage node junction, and which will provide both adequate field isolation and adequate punchthrough protection for short channel transistors.